1. Field of the Invention
This invention relates to the automated design of computer packages, and in particular to a method of optimally using limited interconnection resources, such as hybrid interconnection pins or wiring tracks on the computer package, to make connections to inputs and outputs on differential current switch logic elements.
2. Description of Related Art
The design of integrated computer packages in which multiple logic inputs and outputs must be interconnected has been greatly simplified through the use of automated design tools embodied in software. Such tools enable the designer to optimally use limited interconnection resources to make necessary connections. The interconnection resources may be wiring pins, vias, wiring tracks or other interconnection resources that are limited in number or by physical or design restrictions. The function of such software design tools is to determine a way of assigning the limited resources to respective requirements so as to globally optimize their use.
Examples of previous automated design tools include pin assignment programs and routing programs. Pin assignment programs assign connection points to destinations by matching input output connection points on logic chips to a specific one of many different interconnection pins that they might use. Routing programs assign routing paths to requirements that points and destinations be interconnected by selecting a specific one of many different possible wiring tracks that lead from a point to a destination. Such tools, however, were developed for use with conventional logic families such as emitter coupled logic (ECL), transistor logic (TTL) and the like. These logic families share certain similarities because the fundamental binary switch that each logic element is constructed from has a single electrical input and a single electrical output.
For example, ECL logic, which is widely used in high performance computer packages, has a pair of transistors forming its fundamental binary logic switch which steer current in one of two directions to give the two binary states of the switch. The base of one o the transistors is connected to a reference voltage and the input to the switch is connected to the base of the other transistor. When the voltage at the input is above the reference voltage, the current is steered in one direction, and when it is below the reference voltage, it is steered in the other.
The desire for fast, low power logic circuitry has led to the development of a low power variation of emitter coupled logic called differential current switch (DCS). The DCS logic family uses differential signal pairs to represent logic signals and requires two inputs for each basic logic switch. The DCS logic switch is similar to the ECL logic switch in that it uses a pair of transistors that steer current in one of two directions to define the binary state of the switch. However, it has two inputs to each logic gate, connected to the bases of the two transistors.
To change the state of the DCS logic element, one of the inputs is driven high and the other is simultaneously driven low. The advantage to using twin inputs carrying complementary signals is that the DCS signal swing can be reduced to less than 50% of the ECL signal swing while retaining the same reliable switching as the ECL logic family. This provides improved speed and decreased power consumption at the cost of increasing circuit complexity by doubling the number of wires and interconnection points for each logic gate.
In some designs this complexity is acceptable, as it results in improved performance and reduced power dissipation. This is particularly desirable in high-speed computers that are air cooled. However, present automated design tools are not well suited to designing computer packages that use DCS logic because the dual input/dual output logic introduces complexities not found in single input/single output logic families.
Since both a signal and its complementary phase must be carried in DCS logic, all interconnections are carried between the gates on two separate paths called "rails". The interconnections between the logic elements on the rails are generally referred to as a "DCS net". In the design of a DCS net, to insure reliable switching, the following conditions have to be satisfied for the two signals to maintain their relative phases and magnitudes when they arrive at the receiver:
1. The electrical length of both rails should be the same; and PA1 2. Each rail should be exposed to the same electrical environment, such as noise effects. PA1 1. The two rails should have the same length within a certain tolerance; and PA1 2. The two rails should be routed next to each other as far as possible.
In most practical designs, these requirements translate into the following restrictions:
These design limitations are distinctly different from the limitations that apply when designing a computer package for use with logic families that include only a single input. In the design of computer packages using single input/single output logic families, the assignment of an interconnection resource, such as an available interconnection pin or wiring track, to an input or output on a logic chip is assumed to be relatively independent of the assignments of the other resources. Thus, assignments can be calculated individually for each requirement in any order to achieve a globally optimum solution for use of the resources.
In the automated design of a computer package containing DCS logic, however, the limitations above introduce an order dependence into the problem. Conventional automated design tools may find an optimal path for one of the two rails, but the second rail must then be routed in accordance with the above strict requirements. This often results in a nonoptimal assignment globally.
The present invention provides a method for using pre-existing automated design tools and algorithms developed for single input/output logic families to optimally assign interconnection resources (interconnection pins and available wiring tracks) to the dual input/output connection points on DCS logic chips.
While the invention may be used in connection with the automated design of any package incorporating logic using complementary or paired signals, it is particularly described in connection with DCS logic when used in the manufacture of thermal conducting modules (TCMs) in large mainframe computers where the interconnection assignment task is particularly complex and the optimal use of limited interconnection resources is particularly important.
Thermal conducting modules are a type of multi-chip carrier used in high performance computers in which multiple logic chips are integrated into a single package. Originally, TCMs were designed with only one type of wiring media. However, they are now being designed with two types of wiring media, thin film and glass ceramic. A certain number of wiring layers are constructed with thin film and the others with glass ceramic. The logic chips are located at the uppermost layer on top of one or more thin film wiring layers which make connection to the logic chips. Below the thin film layers are one or more glass ceramic wiring layers.
The thin film layers make contact to the inputs and outputs (generically referred to herein as input/output connection points) on the DCS chips. A wire formed on the thin film layer runs horizontally from this connection point to an interconnection pin. The pin penetrates vertically down through the thin film layers to the appropriate glass ceramic layer. Another wire formed on the glass ceramic layer runs across the layer to a second interconnection pin which brings the signal up to another thin film layer and from there to its destination.
The glass ceramic layers are mounted to a substrate which may be air or liquid cooled. TCMs are usually designed with regular grids for the wiring and pins. The pin grid on the thin film layer, however, is much finer than the pin grid on the glass ceramic layer. Typically, the grid pitch on the glass ceramic is twice that on the thin film. Hence, there are only a small number of interconnection pins, referred to as "hybrid pins", which connect the two media.
All connections being wired in glass ceramic have to use a hybrid pin to get down to the glass ceramic layers from the top surface. Since a large amount of the wiring is typically done in glass ceramic, quite a few connections need to use these hybrid pins. There are also other uses for the pins such as bringing power to the chips. Accordingly the hybrid pins are a very scarce resource which must be used in an optimal fashion. If the assignment is not optimal, some pins may end up being unusable because they will be too far from or too close to an input/output connection point that needs to use them, or otherwise fail to meet some limitation on their use that might have been satisfied if a better assignment method had been used.
Conventional automated design tools fail to achieve the desired optimization when assigning interconnection resources for use by DCS nets because of the order dependence introduced by the paired wiring of DCS logic. Typical pin assignment and routing algorithms work on a one-connection-at-a-time basis. The pin assigned or the available wiring track selected is decided during the routing process for each connection. If that methodology is followed in a DCS chip design, however, the hybrid pin used by each connection to enter the glass ceramic layer will be determined as it is routed.
This approach leads to a globally non-optimal solution, even though an optimal solution may be found for a particular connection. Also, no consideration can be given to the relative difficulty of the constraints on different connections, except by the order in which they are routed.
In addition to providing a method of using existing automated design tools to achieve globally optimal solutions for interconnection resource assignment, the present invention is directed to a simplified method for DCS wiring which breaks the design problem into a first stage in which the DCS input/output connection points are assigned to the scarce resource hybrid pins, and a second step in which routing of wiring tracks occurs.
The task of optimally using interconnection resources to make connections on a TCM between the output of a logic gate on one DCS chip and the input to a logic gate on another DCS chip involves a series of paired decisions as to how to use resources subject to certain requirements. Four hybrid pins need to be assigned, two to the paired outputs of the first logic gate and two to the paired inputs of the second gate. Four wiring tracks on the thin film layer need to be assigned, two from the paired inputs to their assigned pins, and two from the paired outputs to their pins. Finally, a pair of wiring tracks on the ceramic wiring layer need to be assigned, from the pins assigned to the inputs to the pins assigned to the outputs.
In each case there are certain limitations on the assignments. One set of limitations is due to physical constraints that apply regardless of the fact that a DCS pair is being assigned. These are limitations such as minimum and maximum distances from a connection point to its assigned hybrid pin. These limitations apply in the assignment of resources in the design of a TCM based on conventional logic families, as well as in DCS designs. Conventional design tools handle these limitations well.
The other limitations are due to the DCS restrictions that the rails be of equal length and routed closely together. Previous design tools do not perform well in making assignments subject to these types of restrictions. The present invention, however, provides a method of adapting prior art design tools developed for single I/O logic families for use in DCS logic design tasks.
Bearing in mind the problems and deficiencies in the prior art, it is therefore an object of the present invention to provide a method of automated design of computer packages incorporating differential current switch logic elements.
It is another object of the present invention to provide a method of automated design which adapts previous methods of routing and pin assignment algorithms and procedures developed for single I/O logic families for use with DCS paired I/O logic.
It is still another object of the present invention to provide a method of optimally assigning hybrid pins to DCS input/output connection points.